PaperSingle-event upsets and multiple-bit upsets on a 45 nm SOI SRAMDavid F. Heidel, Paul W. Marshall, et al.IEEE TNS
PaperImplementation of a self-resetting CMOS 64-bit parallel adder with enhanced testabilityWei Hwang, George Diedrich Gristede, et al.IEEE Journal of Solid-State Circuits
PaperSingle-event upsets and multiple-bit upsets on a 45 nm SOI SRAMDavid F. Heidel, Paul W. Marshall, et al.IEEE TNS
PaperSingle-event-upset critical charge measurements and modeling of 65 nm silicon-on-insulator latches and memory cellsDavid F. Heidel, Kenneth P. Rodbell, et al.IEEE TNS
