A High-Performance 0.25-μm CMOS Technology: I—Design and Characterization

Abstract

A high-performance 0.25-μm-channel CMOS technology is designed and characterized. The technology utilizes n⁺ polysilicon gate on nFET and p⁺ polysilicon gate on pFET so that both FET's are surface channel devices. The gate oxide thickness is 7 nm. Abrupt As and B source/drain junctions with reduced power supply voltage are used to achieve high-speed operation. The technology yields a loaded ring oscillator (NAND, FI = FO = 3, C<inf>w</inf>= 0.2 pF) delay per stage of 280 ps at W<inf>eff</inf>/L<inf>eff</inf> = 15 μm/0.25 μm, which is a 1.7 × improvement over 0.5-μm CMOS technology. At shorter channel length of 0.18 μm, a CMOS stage delay of 38 ps for unloaded inverter and 185 ps for loaded NAND ring oscillators are measured. Key design issues of the CMOS devices are discussed. © 1992 IEEE