IEDM 1991
Conference paper

A full E-beam 0.25 mu m bipolar technology with sub-25 ps ECL gate delay

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Summary form only given. The full leverage offered by E-beam lithography has been exploited in a 0.25- mu m bipolar process. The tight overlay capability was shown to provide a significant advantage in shrinking the overall transistor size. In conjunction with a device technology optimized to provide a 33-GHz 0.25- mu m-emitter device, this culminated in the achievement of an ECL (emitter coupled logic) delay of 24 ps at a switching current of only 1.1 mA.