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IEEE TCAS-I
A 23.5 GHz 32 nm SOI-CMOS PLL with 30% frequency tuning range features an adaptively biased VCO. The adaptive biasing scheme lowers the average PLL power consumption from 34 mW to 27.2 mW, while keeping the jitter below 1.3° RMS across all frequency bands. © 2004-2012 IEEE.
Shupeng Sun, Fa Wang, et al.
IEEE TCAS-I
Jonghae Kim, Jean-Olivier Plouchart, et al.
IEDM 2003
Mehmet Soyuer, Herschel A. Ainspan, et al.
Proceedings of the IEEE
Jean-Olivier Plouchart, Noah Zamdmer, et al.
IEEE Transactions on Electron Devices