Bodhisatwa Sadhu, Mark A. Ferriss, et al.
RFIC 2012
Paper
A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS
Abstract
A 23.5 GHz 32 nm SOI-CMOS PLL with 30% frequency tuning range features an adaptively biased VCO. The adaptive biasing scheme lowers the average PLL power consumption from 34 mW to 27.2 mW, while keeping the jitter below 1.3° RMS across all frequency bands. © 2004-2012 IEEE.
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