Asaf Tzadok, Alberto Valdes-Garcia, et al.
IMS 2020
A 23.5 GHz 32 nm SOI-CMOS PLL with 30% frequency tuning range features an adaptively biased VCO. The adaptive biasing scheme lowers the average PLL power consumption from 34 mW to 27.2 mW, while keeping the jitter below 1.3° RMS across all frequency bands. © 2004-2012 IEEE.
Asaf Tzadok, Alberto Valdes-Garcia, et al.
IMS 2020
Scott K. Reynolds, Arun S. Natarajan, et al.
RFIC 2010
Jean-Olivier Plouchart, Jonghae Kim, et al.
IEDM 2005
Jonghae Kim, Jean-Olivier Plouchart, et al.
ISLPED 2003