300 mm SGOI/strain-Si for high-performance CMOS

Abstract

The development of 300 mm strained SGOI/strain-Si material technology for fabrication of high-performance CMOS substrates, was investigated. Delineation of crystallographic defects by a quick turn around technique, which utilizes optical microscopy in conjunction with defect etching was developed. The key parameter which determines the carrier mobility enhancement in strain Si is the magnitude of tensile strain in the top Si layer. Under this investigation, typical relaxation values were targeted to achieve 0.5-0.6% strain in Si. The results show that key physical properties of the final SGOI layer can be accurately predicted based on the knowledge of the initial structure and subsequent processing.