Accepted Posters
- L. Alt, G. Fedyukovich, A. E. J. Hyvarinen, and N. Sharygina
A Proof-Sensitive Approach for Small Propositional Interpolants
- Michael Bar-Sinai, Assaf Marron, and Gera Weiss
A Behavioral-Programming Based Architecture for Heterogeneous, Verifiable and Executable Requirements
- Nimrod Busany and Shahar Maoz
Behavioral Log Analysis with Statistical Guarantees
- Ondrej Cekan and Zkenek Kotasek
Assembly Program Generation for Processors
- Jonathan Kalechstain, Vadym Ryvchin, and Nachum Dershowitz
Using Hints to Speed-Up SAT
- Rajdeep Mukherjee
Abstract CDCL for Hardware Verification
- Heinrich Kiessling, Martin Nowack, Frank Busse, and Christof Fetzer
Improving Cache Efficiency of Symbolic Execution
