Keynote Speakers

Title: Fight for the Future of Verification; Live In It Today
Stephen Bailey, Director of Emerging Technologies, Mentor Graphics

Abstract
Functional verification is arguably the #1 challenge in the semiconductor and, therefore, EDA industries today. The pressure to verify ever larger, more complex systems within the context of schedules squeezed by market demands is tremendous. While it is impossible to predict specific inventions or innovations to come, it is possible to identify the challenges they must solve by understanding what is or will be consuming the most verification time. Specific areas of exploration include moving beyond chip to system level verification, SoC architectural implications on verification cycles and methodology and tying big data into verification automation.

Speaker Bio
As Director of Emerging Technologies, Stephen Bailey seeks out and develops new technology, solutions and business opportunities in functional verification and related areas. He brings many years of industry experience working in R&D, applications and technical and product marketing. He has contributed to the industry through participation in industry standards, including chairing VHDL (IEEE 1076) and UPF (IEEE 1801) working groups, and serving in various roles from member of technical program committee to conference chair with conferences such as DVCon. Prior to joining the EDA industry, Steve developed embedded software and software development tools. Steve has BS and MS degrees in computer science from Chapman University.