Demonstration of Reliable Triple-Level-Cell (TLC) Phase-Change Memory
- Milos Stanisavljevic
- Haralampos Pozidis
- et al.
- 2016
- IMW 2016
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4 results at IMW 2016
A Double-Data-Rate 2 (DDR2) Interface Phase-Change Memory with 533MB/s Read-Write Data Rate and 37.5ns Access Latency for Memory-Type Storage Class Memory Applications
- H. Lung
- C. Miller
- et al.
- 2016
- IMW 2016
Effect of Read Disturb on Incomplete Blocks in MLC NAND Flash Arrays
- Nikolaos Papandreou
- Thomas Parnell
- et al.
- 2016
- IMW 2016
Carbon-Based Resistive Memories
- Wabe W. Koelmans
- Tobias Bachmann
- et al.
- 2016
- IMW 2016