Functional high-speed characterization and modeling of a six-layer copper wiring structure and performance comparison with aluminum on-chip interconnections
- A. Deutsch
- H. Harrer
- et al.
- 1998
- IEDM 1998
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9 results at IEDM 1998
Scalability of SOI technology into 0.13 μm 1.2 V CMOS generation
- E. Leobandung
- M. Sherony
- et al.
- 1998
- IEDM 1998
Straddle-gate transistor: Changing MOSFET channel length between off- and on-state towards achieving tunneling-defined limit of field-effect
- S. Tiwari
- J.J. Welser
- et al.
- 1998
- IEDM 1998
High-performance sub-0.08 μm CMOS with dual gate oxide and 9.7 ps inverter delay
- M. Hargrove
- S.W. Crowder
- et al.
- 1998
- IEDM 1998
Progress in RF inductors on silicon - understanding substrate losses
- J.N. Burghartz
- 1998
- IEDM 1998
25 nm CMOS design considerations
- Y. Taur
- C. Wann
- et al.
- 1998
- IEDM 1998
Reliability projection for ultra-thin oxides at low voltage
- J.H. Stathis
- D.J. DiMaria
- 1998
- IEDM 1998
Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation
- H.-S. Wong
- David J. Franks
- et al.
- 1998
- IEDM 1998
Within-chip variability analysis
- S. Nassif
- 1998
- IEDM 1998