Design of Analog-AI Hardware Accelerators for Transformer-based Language Models (Invited)Geoffrey BurrSidney Tsaiet al.2023IEDM 2023
SyncTREE: Fast Timing Analysis for Integrated Circuit Design through a Physics-informed Tree-based Graph Neural NetworkYuting HuJiajie Liet al.2023NeurIPS 2023
Evaluation of (110) versus (001) Channel Orientation for Improved nFET/pFET Device Performance Trade-Off in Gate-All-Around Nanosheet TechnologyShogo MochizukiNicolas Loubetet al.2023IEDM 2023
In-Memory Compute Chips with Carbon-based Projected Phase-Change Memory DevicesG.S. SyedK. Brewet al.2023IEDM 2023
Scaling opportunities for Gate-All-Around and beyond: A patterning perspectiveIndira SeshadriEric Milleret al.2023IEDM 2023
Reversing a decades-long scaling law of dielectric breakdown for ReRAM forming voltage reduction - Modeling competition among defect generation and annihilation processesErnest Y WuTakashi Andoet al.2023IEDM 2023
Synapses, Circuits, and Architectures for Analog In-Memory Computing-Based Deep Neural Network Inference Hardware AccelerationIrem Boybat-Kara2023IEDM 2023
Design of synchronous frequency dividers in 5-nm FinFET CMOS technologyMarcel KosselPier Andrea Franceseet al.2023Electronics Letters
Using the IBM Analog In-Memory Hardware Acceleration Kit for Neural Network Training and InferenceManuel Le GalloCorey Liam Lammieet al.2023APL Mach. Learn.