Design considerations for PD/SOI SRAM: Impact of gate leakage and threshold voltage variation
- Rouwaida Kanj
- Rajiv V. Joshi
- et al.
- 2008
- IEEE Trans Semicond Manuf
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Decomposition and analysis of process variability using constrained principal component analysis
- Ongyeun Cho
- Daeik D. Kim
- et al.
- 2008
- IEEE Trans Semicond Manuf
Ring oscillators for CMOS process tuning and variability control
- Manjul Bhushan
- Anne Gattiker
- et al.
- 2006
- IEEE Trans Semicond Manuf
Capacity planning under demand uncertainty for semiconductor manufacturing
- Sarah Jean Hood
- Stuart Bermon
- et al.
- 2003
- IEEE Trans Semicond Manuf
High yielding self-aligned contact-process for a 0.150-μm DRAM technology
- Thomas S. Rupp
- David Dobuzinsky
- et al.
- 2002
- IEEE Trans Semicond Manuf
The mask error factor in optical lithography
- Alfred K. Wong
- Richard A. Ferguson
- et al.
- 2000
- IEEE Trans Semicond Manuf
Level-specific lithography optimization for 1-Gb DRAM
- Alfred K. Wong
- Richard Ferguson
- et al.
- 2000
- IEEE Trans Semicond Manuf
A queueing network model for semiconductor manufacturing
- Daniel P. Connors
- Gerald E. Feigin
- et al.
- 1996
- IEEE Trans Semicond Manuf
Methods for job configuration in semiconductor manufacturing
- Daniel P. Connors
- David D. Yao
- 1996
- IEEE Trans Semicond Manuf
Integrated Processing of MOS Gate Dielectric Structures
- G.W. Rubloff
- M. Offenberg
- et al.
- 1994
- IEEE Trans Semicond Manuf