A Wide Dynamic Range Sparse FC-DNN Processor with Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET
- Saekyu Lee
- Paul N. Whatmough
- et al.
- 2018
- ESSCIRC 2018
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16 results for Gu-Yeon Wei
Very low voltage (VLV) design
- Ramon Bertran
- Pradip Bose
- et al.
- 2017
- ICCD 2017
Area efficient phase calibration of a 1.6 GHz multiphase DLL
- Ankur Agrawal
- Pavan Kumar Hanumolu
- et al.
- 2011
- CICC 2011
A 7.5-GS/s 3.8-ENOB 52-mW flash ADC with clock duty cycle control in 65nm CMOS
- Hayun Chung
- Alexander Rylyakov
- et al.
- 2009
- VLSI Circuits 2009
CHIPKIT: An Agile, Reusable Open-Source Framework for Rapid Test Chip Development
- Paul N. Whatmough
- Marco Donato
- et al.
- 2020
- IEEE Micro
A 7.5 GS/s flash ADC and a 10.24 GS/s time-interleaved ADC for backplane receivers in 65 nm CMOS
- Hayun Chung
- Zeynep Toprak-Deniz
- et al.
- 2015
- Analog Integr Circuits Signal Process