Publication
CICC 2011
Conference paper

Area efficient phase calibration of a 1.6 GHz multiphase DLL

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Abstract

This paper describes a digital calibration scheme that corrects for phase spacing errors in a multiphase clock generating delay-locked loop (DLL). The calibration scheme employs sub-sampling using a frequency-offset clock with respect to the DLL reference clock, to measure phase-offsets. The phase-correction circuit uses one digital-to-analog converter across eight variable-delay buffers to reduce the area consumption by 62%. The test-chip, designed in a 130nm CMOS process, demonstrates a 8-phase 1.6 GHz DLL with a worst-case phase error of 450 fs. © 2011 IEEE.

Date

09 Nov 2011

Publication

CICC 2011

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