A 400-ns-Settling Time Hybrid Dynamic Voltage Frequency Scaling Architecture and Its Application in a 22-Core Network-on-Chip SoC in 12-nm FinFET Technology
- Erik Loscalzo
- Martin Cochet
- et al.
- 2024
- VLSI Technology and Circuits 2024
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16 results for Gu-Yeon Wei
A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration
- Maico Cassel Dos Santos
- Tianyu Jia
- et al.
- 2024
- ISSCC 2024
Co-designing accelerators and SoC interfaces using gem5-Aladdin
- Yakun Sophia Shao
- Sam Likun Xi
- et al.
- 2016
- MICRO 2016
Quantifying sources of error in McPAT and potential impacts on architectural studies
- Sam Likun Xi
- Hans Jacobson
- et al.
- 2015
- HPCA 2015
Tribeca: Design for PVT variations with local recovery and fine-grained adaptation
- Meeta S. Gupta
- Jude A. Rivers
- et al.
- 2009
- MICRO 2009
SMIV: A 16-nm 25-mm SoC for IoT With Arm Cortex-A53, eFPGA, and Coherent Accelerators
- Sae Kyu Lee
- Paul N. Whatmough
- et al.
- 2022
- IEEE JSSC
DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications
- Paul N. Whatmough
- Saekyu Lee
- et al.
- 2018
- IEEE JSSC
A scalable methodology for agile chip development with open-source hardware components
- Maico Cassel Dos Santos
- Tianyu Jia
- et al.
- 2022
- ICCAD 2022
A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC
- Tianyu Jia
- Paolo Mantovani
- et al.
- 2022
- ESSCIRC 2022
A 16nm 25mm2 SoC with a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to eFPGA and Cache-Coherent Accelerators
- Paul N. Whatmough
- Saekyu Lee
- et al.
- 2019
- VLSI Circuits 2019