Gate Resistance Test Structures Bounded by Local Layout Density to Characterize Metal Gate Height Variation in 7nm FinFET Technology

Abstract

Metal gate height (MGH) control is a critical mission in 7nm FinFET process. Gate lateral resistance, usually measured on a four-terminal test structure, is a convenient indicator of gate height. This abstract demonstrates the successful application of a set of gate resistance test structures with various local gate densities that discovered MGH variability systematics as a yield detractor in chip products, facilitated process improvement, and guided chip design optimization. They also exemplify effective process monitors that stay relevant to the context of product design.