High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET
- K. Cheng
- A. Khakifirooz
- et al.
- 2012
- IEDM 2012
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35 results for Nancy Klymko
A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid cu-adhesive bonding
- F. Liu
- R.R. Yu
- et al.
- 2008
- IEDM 2008
Systematic characterization of pseudomorphic (110) intrinsic SiGe epitaxial films for hybrid orientation technology with embedded SiGe source/drain
- Qiqing Ouyang
- Anita Madan
- et al.
- 2006
- MRS Spring Meeting 2006
Fabrication and Mobility Characteristics of Ultra-thin Strained Si Directly on Insulator (SSDOI) MOSFETs
- K. Rim
- K.K. Chan
- et al.
- 2003
- IEDM 2003
Aggressively scaled strained-silicon-on-insulator undoped-body High-κ/Metal-Gate nFinFETs for high-performance logic applications
- Kingsuk Maitra
- Ali Khakifirooz
- et al.
- 2011
- IEEE Electron Device Letters
Bottom oxidation through STI (BOTS) - A novel approach to fabricate dielectric isolated FinFETs on bulk substrates
- K. Cheng
- S.-C. Seo
- et al.
- 2014
- VLSI Technology 2014
Ultrathin (8-14 nm) conformal SiN for sub-20 nm Copper/Low-k Interconnects
- Son Van Nguyen
- Deepika Priyadarshini
- et al.
- 2014
- ECS Meeting 2014
Atomic layer deposition of sidewall spacers: Process, equipment and integration challenges in state-of-the-art logic technologies
- Michael Belyansky
- Richard Conti
- et al.
- 2014
- ECS Meeting 2014
Cu-based bonding technology for 3D integration applications
- K.N. Chen
- Zheng Xu
- et al.
- 2012
- 3DIC 2012
Optimization of porous ultra low- dielectrics (κ≤ 2.55) for 28nm generation
- D. Kioussis
- E.T. Ryan
- et al.
- 2011
- IITC/MAM 2011