A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
Publications
Date
Featured collections
Popular topics
9 results for C. Surisetty
Air spacer for 10nm FinFET CMOS and beyond
- K. Cheng
- C. Park
- et al.
- 2016
- IEDM 2016
Highly-selective superconformai CVD Ti silicide process enabling area-enhanced contacts for next-generation CMOS architectures
- Nicolas Breil
- A. Carr
- et al.
- 2017
- VLSI Technology 2017
CMP: Consideration of stop-on selectivity in advanced node semiconductor manufacturing technology
- Stan Tsai
- Hari Amanapu
- et al.
- 2017
- ECS Meeting 2017 - New Orleans
Tungsten and cobalt metallization: A material study for MOL local interconnects
- Vimal Kamineni
- Mark Raymond
- et al.
- 2016
- IITC/AMC 2016
Bottom oxidation through STI (BOTS) - A novel approach to fabricate dielectric isolated FinFETs on bulk substrates
- K. Cheng
- S.-C. Seo
- et al.
- 2014
- VLSI Technology 2014
Formation mechanism and suppression methods of copper dendrites in BEOL integration
- Shaoning Yao
- Wei-Tsu Tseng
- et al.
- 2011
- ADMETA 2011
CMP Challenges for Advanced Technology Nodes
- John H Zhang
- Haigou Huang
- et al.
- 2017
- MRS Advances
Experimental study of copper leveling additives and their wafer and pattern-scale effect on copper planarization
- James Kelly
- Charan Surisetty
- et al.
- 2013
- Comptes Rendus Chimie