Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation
- H.-S. Wong
- David J. Franks
- et al.
- 1998
- IEDM 1998
Publications
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114 results for H.-S. Philip Wong
Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel
- H.-S. Wong
- K.K. Chan
- et al.
- 1997
- IEDM 1997
CMOS image sensors - recent advances and device scaling considerations
- H.-S. Wong
- 1997
- IEDM 1997
Probing the limits of silicon-based nanoelectronics
- S.J. Wind
- Y. Taur
- et al.
- 1995
- MRS Spring Meeting 1995
Design and performance considerations for sub-0.1 μm double-gate SOI MOSFETs
- H.-S. Wong
- D.J. Frank
- et al.
- 1994
- IEDM 1994
Three-Dimensional “Atomistic” Simulation of Discrete Random Dopant Distribution Effects in Sub-0.1μm MOSFET's
- Hon-Sum Wong
- Yuan Taur
- 1993
- IEDM 1993
INVESTIGATION OF HOT ELECTRON LUMINESCENCE IN SILICON BY MEANS OF DUAL-GATE MOSFET's
- Luca Selmi
- Hon-Sum Wong
- et al.
- 1993
- IEDM 1993
Gate-current injection and surface impact ionization in MOSFET's with a gate induced virtual drain
- Hon-Sum Wong
- 1992
- IEDM 1992
Experimental verification of the mechanism of hot-carrier-induced photon emission in n-MOSFET's with a CCD gate structure
- Hon-Sum Wong
- 1991
- IEDM 1991
Analog Coding in Emerging Memory Systems
- Ryan V. Zarcone
- Jesse H. Engel
- et al.
- 2020
- Scientific Reports