On the location and magnitude of trapped charge in poly- Si ALD-Al 2O3 capped Hf-silicate gate stacks
- Kingsuk Maitra
- Barry P. Linder
- et al.
- 2005
- PRiME/ECS Meeting 2005
Conference paper
Publications
206 results for Vijay Narayanan
Ultra-thin SOI replacement gate CMOS with ALD TaN / high-k gate stack
- B. Doris
- B.P. Linder
- et al.
- 2005
- VLSI-TSA 2005
Conference paperPoly-Si/high-k gate stacks with near-ideal threshold voltage and mobility
- M.M. Frank
- V.K. Paruchuri
- et al.
- 2005
- VLSI-TSA 2005
Conference paperPotential imaging of Si/HfO2/polycrystalline silicon gate stacks: Evidence for an oxide dipole
- R. Ludeke
- V. Narayanan
- et al.
- 2005
- Applied Physics Letters
PaperEvaluation of thermal stability for CMOS gate metal materials
- C. Cabral Jr.
- C. Lavoie
- et al.
- 2004
- JES
PaperAdvanced gate stacks with fully silicided (FUSI) gates and high-κ dielectrics: Enhanced performance at reduced gate leakage
- E. Gusev
- C. Cabral Jr.
- et al.
- 2004
- IEDM 2004
Conference paperCharge trapping in aggressively scaled metal gate/high-κ stacks
- E. Gusev
- V. Narayanan
- et al.
- 2004
- IEDM 2004
Conference paperInterface engineering for enhanced electron mobilities in W/HfO 2 gate stacks
- A.C. Callegari
- P. Jamison
- et al.
- 2004
- IEDM 2004
Conference paperThermally robust dual-work function ALD-MN x MOSFETs using conventional CMOS process flow
- D.-G. Park
- Z. Luo
- et al.
- 2004
- VLSI Technology 2004
Conference paperSystematic study of pFET Vt with Hf-based gate stacks with poly-Si and FUSI gates
- E. Cartier
- V. Narayanan
- et al.
- 2004
- VLSI Technology 2004
Conference paper