Publications

92 results for Ruchir Puri

Scaling planar silicon devices
- - Ching-Te Chuang
  - Kerry Bernstein
  - et al.
- 2004
- IEEE Circuits and Devices Magazine
An Integrated Environment for Technology Closure of Deep-Submicron IC Designs
- - Louise Trevillyan
  - David Kung
  - et al.
- 2004
- IEEE Design and Test of Computers
Regular logic fabrics for a via patterned gate array (VPGA)
- - K.Y. Tong
  - V. Kheterpal
  - et al.
- 2003
- CICC 2003
Design and CAD Challenges in sub-90nm CMOS Technologies
- - Kerry Bernstein
  - Ching-Te Chuang
  - et al.
- 2003
- ICCAD 2003
Hysteresis effect in floating-body partially depleted SOI CMOS domino circuits
- - Ruchir Puri
  - Ching-Te Chuang
- 2003
- International Journal of Electronics
Effects of gate-to-body tunneling current on PD/SOI CMOS latches
- - C.T. Chuang
  - R. Puri
- 2003
- SISPAD 2003
Pushing ASIC performance in a power envelope
- - Ruchir Puri
  - Leon Stok
  - et al.
- 2003
- DAC 2003
Design considerations of scaled sub-0.1 μm PD/SOI CMOS circuits
- - C.T. Chuang
  - R.V. Joshi
  - et al.
- 2003
- ISQED 2003
Effects of gate-to-body tunneling current on pass-transistor based PD/SOI CMOS circuits
- - C.T. Chuang
  - R. Puri
- 2002
- IEEE International SOI Conference 2002
Fast and accurate wire delay estimation for physical synthesis of large ASICs
- - Ruchir Puri
  - David S. Kung
  - et al.
- 2002
- GLSVLSI 2002