Effects of gate-to-body tunneling current on PD/SOI CMOS latches
- C.T. Chuang
- R. Puri
- 2003
- SISPAD 2003
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87 results for Ruchir Puri
Pushing ASIC performance in a power envelope
- Ruchir Puri
- Leon Stok
- et al.
- 2003
- DAC 2003
Design considerations of scaled sub-0.1 μm PD/SOI CMOS circuits
- C.T. Chuang
- R.V. Joshi
- et al.
- 2003
- ISQED 2003
Effects of gate-to-body tunneling current on pass-transistor based PD/SOI CMOS circuits
- C.T. Chuang
- R. Puri
- 2002
- IEEE International SOI Conference 2002
Fast and accurate wire delay estimation for physical synthesis of large ASICs
- Ruchir Puri
- David S. Kung
- et al.
- 2002
- GLSVLSI 2002
Measurement of history effect in PD/SOI single-ended CPL circuit
- Keith A. Jenkins
- R. Puri
- et al.
- 2001
- IEEE International SOI Conference 2001
On the temperature dependence of hysteresis effect in floating-body partially depleted SOI CMOS circuits
- R. Puri
- C.T. Chuang
- et al.
- 2001
- IEEE Journal of Solid-State Circuits
Hysteresis Effect in Pass-Transistor-Based, Partially Depleted SOI CMOS Circuits
- Ruchir Puri
- Ching-Te Chuang
- 2000
- IEEE Journal of Solid-State Circuits
SOI digital circuits: design issues
- R. Puri
- C.T. Chuang
- 2000
- VLSID 2000
Combinatorial cell design for CMOS libraries
- Frederik Beeftink
- Prabhakar Kudva
- et al.
- 2000
- Integration, the VLSI Journal