Effects of gate-to-body tunneling current on PD/SOI CMOS latches

Abstract

This paper presents a detailed study on the effect of gate-to-body tunneling current on PD/SOI CMOS latches. The physical mechanism and its impact on the initial quiescent states and performance of the latches are analyzed. It is shown that the effect on latch setup time is particularly significant due to the compounding effect of the master-slave configuration.