A learning-based recommender system for autotuning design flows of industrial high-performance processors
- Jihye Kwon
- Matt Ziegler
- et al.
- 2019
- DAC 2019
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13 results for Luca P. Carloni
A 400-ns-Settling Time Hybrid Dynamic Voltage Frequency Scaling Architecture and Its Application in a 22-Core Network-on-Chip SoC in 12-nm FinFET Technology
- Erik Loscalzo
- Martin Cochet
- et al.
- 2024
- VLSI Technology and Circuits 2024
A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration
- Maico Cassel Dos Santos
- Tianyu Jia
- et al.
- 2024
- ISSCC 2024
A 2.5D integrated voltage regulator using coupled-magnetic-core inductors on silicon interposer delivering 10.8A/mm 2
- Noah Sturcken
- Eugene O'Sullivan
- et al.
- 2012
- ISSCC 2012
A 2.5D integrated voltage regulator using coupled-magnetic-core inductors on silicon interposer
- Noah Sturcken
- Eugene J. O'Sullivan
- et al.
- 2013
- IEEE JSSC
A scalable methodology for agile chip development with open-source hardware components
- Maico Cassel Dos Santos
- Tianyu Jia
- et al.
- 2022
- ICCAD 2022
Scalable Auto-Tuning of Synthesis Parameters for Optimizing High-Performance Processors
- Matt Ziegler
- Hung-Yi Liu
- et al.
- 2016
- ISLPED 2016
A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC
- Tianyu Jia
- Paolo Mantovani
- et al.
- 2022
- ESSCIRC 2022
A synthesis-parameter tuning system for autonomous design-space exploration
- Matt Ziegler
- Hung-Yi Liu
- et al.
- 2016
- DATE 2016
A scalable black-box optimization system for auto-tuning VLSI synthesis programs
- Matt Ziegler
- Hung-Yi Liu
- et al.
- 2016
- RES4ANT 2016