Threshold voltage shift (ΔVT) due to negativebias temperature instability (NBTI) in p-FinFETs with replacement metal gate-based high-k metal gate process is measured using an ultrafast method. A comprehensive modeling framework involving uncorrelated contributions from the generation of interface traps (ΔVIT), hole trapping in preexisting (ΔVHT), and generation of new (ΔVOT) bulk insulator traps is used to quantifymeasureddata. Themodel can explain dc stress and recovery data over an extended temperature range (-40°C to 150°C), for different stress and recovery biases. It can explain ac stress and recovery data for different bias, temperature, frequency, and duty cycle. The differences in time kinetics and temperature activation of ΔVIT, ΔVHT, and ΔVOT, and their relative dominance at various experimental conditions are shown. End-of-life NBTI for dc and ac stress is estimated by using the model and compared to prediction from conventional analytical methods.