Hot carrier degradation under DC and AC stress is studied in replacement metal gate (RMG) Si1-xGex (x = 20%) channel p-FinFETs with high-k gate dielectrics. We show that: hot electron injection is the dominant degradation mechanism for low- and mid-Vg biases, which are more representative stress conditions during typical CMOS logic circuit operation. The excessive electron trapping in aggressively scaled SiGe p-FinFETs can reduce the effective channel length and significantly increase the off-state leakage current (Ioff). We also propose an AC test procedure with HCI/NBTI/Off-state HCI stages in each AC cycle, allowing better evaluation of circuit relevant device degradation. It is found that the effect of electrons trapped during HCI can be recovered or masked by the holes induced in subsequent NBTI stress.