The paper examines the factors that affect the formation of delaminations under C4 joints during chip joining. Through multiscale finite element modeling and chip joining experiments we find that two important parameters determining the susceptibility to C4 delaminations (white bumps) are the effective modulus of the low-K levels in the BEOL stack and the thickness of the upper level in the stack that are built in an oxide dielectric. A simple effective spring model is developed to estimate the impact of metal loading at the via and line levels of interconnect structure on the effective modulus of the low-K dielectric stack. The importance of the effective modulus as a parameter controlling white bump formation is confirmed using a purpose built chip in which the effective modulus is modulated in each corner of the chip. Based on the observations from chip joining experiments it is demonstrated that failng BEOL structures can be differentiated from safe structures using a fail/safe map that is constructed using the effective modulus of the low-K levels and the thickness of the oxide levels as the two axes of the map.