Technology scaling of advanced bulk CMOS on-chip ESD protection down to the 32nm node

Abstract

Technology scaling data are presented based on 65nm, 45nm, and the 32nm High-K, metal gate process. Thin oxide NFET parasitic bipolar snapback and gate dielectrics breakdown voltages decrease to 3.2V and 3.6V, respectively. The top concern is to achieve adequate voltage clamping at I/O pads. Continuous improvement in ESD device failure currents per area is found. Vertical metal wiring schemes are needed to overcome wiring resistance challenges. © 2009 ESDA.