Submicron trenching of semiconductor nanostructures

Abstract

We have devised and demonstrated a novel technique for fabricating structures with nanometer scale features in semiconductor heterostructures. The technique is based on definition of nanometer scale patterns by submicron trenches in a GaAs-AlGaAs heterostructure. The depletion of free carriers below the trenches gives rise to very strong electrostatic confinement. This technique avoids the complications associated with the use of negative resist materials and lift-off techniques while minimizing the time required to expose densely packed patterns. Aharonov-Bohm rings fabricated using this technique exhibit interference oscillation larger than any reported previously.