Performance enhancement using conventional stress elements such as stress liners or embedded source/drain is significantly challenged at extremely tight gate pitch, required for 10nm node and beyond. This issue is more pronounced for non-planar architectures such as FinFETs, especially those made on SOI substrates. SiGe has been utilized in CMOS industry, such as IBM SOI 32nm and 22nm generations, as a knob to adjust the PFET threshold voltage and performance enhancement. Prior work on planar ET-SOI-like FETs clearly demonstrates that the built-in compression in strained-Si1-xGex (s-SiGe) layers plays a significant role in the performance of the short channel devices. While higher Ge content SiGe materials can offer lower effective mass and have potential for better transport properties, their reduced bandgap by increasing Ge content brings concern for some CMOS applications, such as increased drain leakage and high off-state current. In this work, we evaluate s-SiGe pFETs fabricated on SOI substrates with moderate Ge fraction, in a FinFET architecture and with aggressively scaled dimensions suitable for 10nm node. We highlight the process challenges as well as short-channel performance, leakage and scalability of s-SiGe FinFETs.