Strained Si surface channel MOSFETS for high-performance CMOS technology

Abstract

The strained silicon surface channel MOSFETs for high performanc CMOS technology were described. The strain induced splitting of the 6-fold degenerate valleys in the conduction band and the heavy/light hole bands in the valence band reduce effective transport mass and carrier scattering, leading to enhanced electron and hole transport in strained silicon. The results of hydrodynamic device simulations show that enhanced high field transport in strained silicon leads to the improvement in peak intrinsic transconductance.