Strain engineering for silicon CMOS technology

Abstract

A comprehensive review of strain layer engineering is presented. The review contains details of various growth processes that are being currently utilized to create globally and locally strain layers on both bulk-Silicon and SOI substrates. Enhancement in device performance by creating global or local strain in the channel of a CMOS transistor is illustrated. A brief description of techniques suitable to characterize strain layers is given. Strain relaxation at small geometries is discussed. Finally, the manufacturability aspects of these new material systems are examined.