Simulation study on channel length scaling of high performance partially depleted metal gate and poly gate SOI MOSFETs

Abstract

In this work, two-dimensional numerical device simulations and 6-stage inverter chain delay calculations are done to examine whether aggressive channel length scaling continually provides transistor performance gain and whether metal gates (MG) offer potential for device scaling over poly gate (PG) for high performance (HP) applications. Our simulation show that for HP application (1) there is an optimized channel length, at which maximum performance gain is obtained both for MG and PG; (2) At short channel length regime (< 46nm), there is no performance gain of QG-MG relative to PG due to lack of carrier confinement, which result in severe sub-threshold slope degradation of QG-MG; (3) BE-MG stacks show 10% gain on a inverter delay over PG. © 2006 IEEE.