SELF-ALIGNED PROCESSES FOR THE GaAs GATE FET.

Abstract

The authors have developed cold gate and refractory gate self-aligned process for the GaAs-based SISFET. Using either of these approaches, they have demonstrated 0. 7- mu m gate length devices with near-zero threshold voltage, transconductance of 280 mS/mm at 300 K and 400 mS/mm at 77 K and low gate leakage. They have also fabricated 23-stage ring oscillators which yielded delays of 35 ps/gate and speed-power products of 10 fj/gate at 300 K.