Japanese Journal of Applied Physics

Scaled III–V-on-Si transistors for low-power logic and memory applications

Download paper


III–V semiconductors, such as indium-rich InGaAs, are promising as replacements for the Si channel in CMOS technology. In this work, we demonstrate a scaled III–V FinFET technology, integrated on Si substrates using a direct wafer bonding technique. Logic performance down to physical gate lengths of 20 nm and fin widths of 15 nm is explored. Narrow-bandgap materials such as these are susceptible to band-to-band tunneling in the off-state, which enhances the parasitic bipolar effect (an accumulation of holes in the channel region). We here examine the use of source and drain spacers to mitigate this effect, showing a two orders of magnitude improvement in the off-state characteristics of scaled III–V FETs. The parasitic bipolar effect can also be beneficial in enabling a memory effect in the FET. In the second part of the work, we explore this effect towards capacitorless 1 T DRAM cells. We show that the use of a quantum well in these devices can enhance retention times and lead to a significant reduction of the power density.


22 Jan 2021


Japanese Journal of Applied Physics