Role of Interfacial Microstructure on Electromigration Behavior of The Hybrid Bonding in 3D Integration

Abstract

The advancement of artificial intelligence (AI) applications requires a high density I/O interconnect between semiconductor chips in order to maximize the speed and enhance the performance of the AI devices. Vertical 3D chip stacking will be essential in such AI chips as they have emerged as a means of both facilitating semiconductor miniaturization and maintaining Moore’s law scaling trend. One promising vertical stacking technique for achieving a fine pitch scaling below 10 μm is the hybrid bonding that enables the concurrent bonding of dielectric layers Si$O_2$ and conductive metal pads (Cu) between the stacked chips. The first step takes place by aligning the top chip to the bottom chip to form the hydrogen bonding between the activated Si$O_2$ surfaces. Subsequent annealing leads to the conversion of the hydrogen bonding into the covalent Si-O-Si bonding through the condensation reaction. Simultaneously, the recessed Cu pads expand due to thermal expansion until the Cu contacts are made between the top and bottom chips. This expansion generates the bonding pressure, thereby resulting in local yielding and creep of the Cu surfaces. Eventually, interdiffusion across the interface and grain growth developed between the top and bottom Cu pads will enable the seamless bonding of the Cu contacts. The purpose of this study is to tailor the temporal evolution of the bonded Cu-Cu interface that plays a significant role in the reliability of the hybrid bonding. The presence of voids, gaps, and misalignment along the interface increases the contact resistance, resulting in current crowding and early electromigration (EM) failure. To assess the reliability, the EM test is set up by using the test structure, where Kelvin probes are constructed with Cu interconnect pads on a top die and a bottom die with the redistribution layers. The test setup subjects a bonded pad pair to high current stressing (up to ~ 20 mA/μ$m^2$ at elevated temperature (up to 250°C), while measuring its resistance with time. Various cross-sectional coupons will be prepared for the hybrid bonded dies using focused-ion beam (FIB) techniques to reveal the interfacial structure and associated void evolution during the current stressing. In this study, we explore the scaling effect of Cu pad diameters (0.8 – 4 μm) and pitch spacings (2 – 10 μm) on the electromigration behavior of the Cu/Si$O_2$ hybrid bonded chips. As the pad size was small (≤ 4 μm), we observed a greater variation among Cu pads for their grain orientation and grain size. For example, our electron backscatter diffraction (EBSD) study revealed Cu pads with a wide range of grain sizes (0.5 μm on average, with a few grains approaching to 2 μm) and a spectrum of grain orientations (dominant with a preferred orientation from 111, 220 or 200 grains, or mixed with these grains). Further, it showed a dominance of special boundaries such as twin (> 60%) and Σ9 (5–10%) over general boundaries on these Cu pads. It will make the bonding quality different from pad to pad in the same chip. The smaller pads also resulted in more misalignment between the top and bottom pads. Therefore, the EM behavior will vary depending on the bonding interfaces generated by these grains and grain boundaries as well as misalignment. This study reports the EM behavior from isolated bonded pads with various microstructures and pad/pitch lengths. Ultimately, it will identify the scaling effect on the EM and microstructural features that can better resist the EM failure in the interconnections made by the hybrid bonding.