Performance comparison of differential static CMOS circuit topologies in SOI technology

Abstract

The performance of various differential static CMOS circuit topologies based on partially-depleted (PD) and dual-gate SOI devices was examined. Both types of devices have Leff = 0.15 μm. The three differential static CMOS topologies are: a standard CMOS logic, the push-pull cascode logic (PPCL), and the complementary pass-transistor logic (CPL). Three cases are considered: partially-depleted device with a standard, bulk-like connection where the body is tied to the supply rail; partially-depleted device with floating body (FB); and dual gate (DG) device where the bottom gate is driven with the top gate simultaneously.