Phaser: Phased methodology for modeling the system-level effects of soft errors

Abstract

This paper presents all overview of Phaser, a toolset and methodology for modeling the effects of sqft errors on the architectural and microarchitectural functionality of a system. The Phaser framework is used to understand the system-level effects of soft-error rates of a microprocessor chip as its design evolves through the phases of preconcept, concept, high-level design, and register-transfer-level design implementation. Phaser represents a strategic research vision that is being proposed as a next-generation toolset for predicting chip-level failure rates and studying reliability-performance tradeoffs during the phased design process. This paper primarily presents Phaser/ M1, the early stage of the predictive modeling of behavior. © Copyright 2008 by International Business Machines Corporation.