Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond

Abstract

A comparative DC and AC performance evaluation between tri-gate FinFETs and gate-all-around nanowire FETs is carried out for potential sub-7nm technology node. The comparative analysis of the intrinsic and parasitic components using the classical drift-diffusion transport and quantization models indicates that a wider and thinner stacked nanosheet-type design can address the issues associated with conventional nanowire devices while demonstrating improved performance relative to FinFET. The optimization of the wire suspension region is found to be critical for Ieff-Ceff performance trade-offs.