As advanced semiconductor technologies continue to shrink, there is a continued need for interconnect performance and variability to keep pace. Traditional area scaling alone cannot control the increased process variation at advanced nodes. We examine the impact that patterning scheme has on the final interconnect resistance, capacitance and RC variability at sub-36nm pitches. Industry standard patterning schemes are evaluated using the Monte Carlo method. Single exposure (direct print), litho-etch-litho-etch, self-Aligned double patterning and self-Aligned quadruple patterning (SAQP) are considered. In the context of these patterning schemes, lithographic variation and spacer thickness uniformity (where applicable) are evaluated.