Publication
IITC/AMC 2016
Conference paper

Interconnect performance and scaling strategy at the 5 nm Node

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Abstract

In this paper, major challenges for 5 nm node BEOL performance are presented. High wire resistance is a key issue for interconnect delay. Accordingly, we focus on potential wire resistance reduction with various architectures and materials. Copper liner thickness was identified as the major knob for increasing Cu areal percent, as compared to increased line aspect ratio and width. Interconnect delay variability is reviewed and analyzed with respect to various patterning techniques.

Date

Publication

IITC/AMC 2016

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