On the temperature dependence of hysteresis effect in floating-body partially depleted SOI CMOS circuits

Abstract

This paper presents a detailed study on the temperature dependence of hysteresis effect in static CMOS circuits and pass-transistor-based circuits with floating-body partially depleted (PD) silicon-on-insulator (SOI) CMOS devices. Basic physical mechanisms underlying the temperature dependence of hysteretic delay variations are examined. It is shown that, depending on the initial state of the circuit, the initial circuit delays have distinct temperature dependence. For steady-state circuit delays, the temperature dependence is dictated solely by the various charge injection/removing mechanisms into/from the body. Use of cross-coupled dual-rail configuration in pass-transistor-based circuits is shown to be effective in compensating and reducing the disparity in the temperature dependence of the delays.