Performance analysis of tapered gate in PD/SOI CMOS technology

Abstract

"Tapered gate" is a device sizing methodology to improve the performance of critical paths in stacked circuit configurations. This paper presents a detailed study on the performance leverage of "taped gate" in a partially-depleted silicon-on-insulator (PD/SOI) technology. It is shown that because the reduced junction capacitance in PD/SOI device renders the series resistance reduction of the lower transistors in the stack more effective, a "tapered gate" in PD/SOI technology has slightly larger improvement in the rising-input delays for the higher pins and slightly larger degradation on the lower pin falling-input delays compared with bulk CMOS technology. The effects are also shown to be more pronounced for low-VT cases. The study demonstrates that "tapered" gate remains a viable device sizing technique/methodology for performance improvement in a PD/SOI technology.