Josephson cross-sectional model experiment

This paper describes the electrical design and evaluation of the Josephson cross-sectional model (CSM) experiment. The experiment served as a test vehicle to verify the operation at liquid-helium temperatures of Josephson circuits integrated in a package environment suitable for high-performance digital applications. The CSM consisted of four circuit chips assembled on two cards in a three-dimensional card-on-board package. The chips (package) were fabricated in a 2.5-μm (5-μm) minimum linewidth Pb-alloy technology. A hierarchy of solder and pluggable connectors was used to attach the parts together and to provide electrical interconnections between parts. A data path which simulated a jump control sequence and a cache access in each machine cycle was successfully operated with cycle times down to 3.7 ns. The CSM incorporated the key components of the logic, power, and package of a prototype Josephson signal processor and demonstrated the feasibility of making such a processor with a sub-4-ns cycle time.