Modeling of switching noise and coupling in multiple chips of 3D TSV-based systems

Abstract

This paper reports on modeling of simultaneous switching noise (SSN) in power distribution network (PDN) for 3D systems, where multiple IC chips are stacked and connected by through-silicon vias (TSVs). The noises generated by current switching during the transition from idle state to active state are analyzed with both on-chip and off-chip PDNs. SSN is decomposed into different frequency components and their characteristics are discussed. The switching noises in active and silent chips are extracted to evaluate the noise interference in a 3D chip stack. Decoupling capacitors and stagger intervals are used to suppress the noise. Modeling the PDN to minimize the switching noise effects based on our hybrid approach is demonstrated to be effective to analyze the 3D PDN and understand the design tradeoffs in 3D architectures.