Ning Lu
ISQED 2008
We present an innovative and comprehensive approach to model the resistance of local interconnect used in finFET technologies. Our parasitic resistance formulas for finFET source/drain regions cover both merged and unmerged fin processes. They have been verified with field solver simulation results, and are found to be accurate over a wide range of parameter values. Our local interconnect resistance model has been used in 14nm finFET technology, and is a critical part of compact models used in both extraction flow and schematic/pre-layout flow.
Ning Lu
ISQED 2008
Ning Lu, Richard A. Wachnik
IEEE TCAS-I
Ning Lu
Active and Passive Electronic Components
Debajit Bhattacharya, Rajiv V. Joshi, et al.
CICC 2014