About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
CICC 2014
Conference paper
TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology
Abstract
With continued scaling of bulk CMOS devices in the nanometer regime, technology computer-aided design (TCAD) assisted extraction of parasitic capacitances has gained importance for predicting the transient behavior of VLSI circuits. In this paper, we present a TCAD structure synthesis and capacitance extraction methodology in a 22nm CMOS process and report parasitic capacitances that affect the oscillation frequency of a 10 GHz voltage-controlled oscillator (VCO). We observe that front-end capacitances are becoming overwhelmingly dominant at nanometer nodes. We quantify the capacitive interactions between the front-end and back-end features using a layer-by-layer capacitance analysis. The estimated frequency tuning range is in agreement with the tuning range of a 22nm VCO hardware.