We present an innovative and comprehensive approach to model the resistance of local interconnect used in FinFET technologies. Our parasitic resistance formulas for FinFET source/drain regions cover both merged and unmerged fin processes. Both simple and composite local interconnect cases are studied. They have been verified with field solver simulation results, and are found to be accurate over a wide range of parameter values. Our local interconnect resistance model has been used in IBM 14 nm SOI FinFET CMOS technology, and is a critical part of compact models used in both extraction flow and schematic/pre-layout flow.