Interlayer cooling utilizing pumped two-phase flow of a chip-to-chip interconnect-compatible dielectric fluid is an enabling technology for future high power 3D (three-dimensional) chip stacks. Development of this approach requires high fidelity and computationally manageable conjugate thermal models. In this paper, a conjugate heat transfer model developed for simulating two-phase flow boiling through chip embedded micron-scale channels is described. This model uses a novel hybrid approach where governing equations for flow-field and convection in the single-phase flow regions (e.g. inlet plenum) as well as that for heat conduction in solids is solved in detail (i.e., full-physics) while in the two-phase flow regions (e.g. micro-channels), a reduced-physics approach is used. Extensive model validation using data from several experiments was performed to quantify the accuracy of this model under different operating conditions.