Metal-gate granularity-induced threshold voltage variability and mismatch in Si gate-all-around nanowire n-MOSFETs

Abstract

The metal-gate granularity-induced threshold voltage (VT) variability and (VT) mismatch in Si gate-all-around (GAA) nanowire n-MOSFETs (n-NWFETs) are studied using coupled 3-D statistical device simulations considering quantum corrected room temperature drift-diffusion transport. The impact of metal-gate crystal grain size on linear and saturation mode VT variability are analyzed. The VT mismatch study predicts lower mismatch figure of merit (AVT) in TiN-gated Si GAA n-NWFETs compared with the reported experimental mismatch data for TiN-gated Si FinFETs.