Timothy O. Dickson, Yong Liu, et al.
VLSI Circuits 2011
Low-power building blocks for a serial transmitter operating up to 86 Gb/s are designed and implemented in a 130-nm SiGe BiCMOS technology with 150-GHz fT SiGe HBT. Design techniques are presented which aim to minimize high-speed building block power consumption. They include lowering the supply voltage by employing a true BiCMOS high-speed logic family, as well as reducing current consumption by trading off tail currents for inductive peaking. A serial transmitter testchip consuming under 1 W is fabricated and operation is verified up to 86 Gb/s at room temperature (92 Gb/s and 71 Gb/s at 0°C and 100°C, respectively). The circuit operates from a 2.5-V supply voltage, which is the lowest supply voltage for circuits at this data rate in silicon technologies reported to date. © 2007 IEEE.
Timothy O. Dickson, Yong Liu, et al.
VLSI Circuits 2011
Timothy O. Dickson, Zeynep Toprak Deniz, et al.
IEEE JSSC
Xiaoxiong Gu, Lavanya Turlapati, et al.
EPEPS 2011
Jonathan E. Proesel, Zeynep Toprak-Deniz, et al.
VLSI Circuits 2017