A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS

Abstract

As data rates in electrical links rise to 56Gb/s, standards are gravitating towards PAM-4 modulation to achieve higher spectral efficiency. Such approaches are not without drawbacks, as PAM-4 signaling results in reduced vertical margins as compared to NRZ. This makes data recovery more susceptible to residual, or uncompensated, intersymbol interference (ISI) when the PAM-4 waveform is sampled by the receiver. To overcome this, existing standards such as OIF CEI 56Gb/s very short reach (VSR) require forward error correction to meet the target link BER of 1E-15. This comes at the expense of higher latency, which is undesirable for chip-to-chip VSR links in compute applications. Therefore, different channel equalization strategies should be considered for PAM-4 electrical links. Employing 1/2-UI (T/2) tap delays in an FFE extends the filter bandwidth as compared to baud- or T-spaced taps [1], resulting in improved timing margins and lower residual ISI for 56Gb/s PAM-4 data sent across VSR channels. While T/2-spaced FFEs have been reported in optical receivers for dispersion compensation [2], the analog delay techniques used are not conducive to designing dense I/O and cannot support a wide range of data rates. This work demonstrates a 56Gb/s PAM-4 transmitter with a T/2-spaced FFE using high-speed clocking techniques to produce well-controlled tap delays that are data-rate agile. The transmitter also supports T-spaced tap delays, ensuring compatibility with existing standards.